Maximum Duty Cycle for Input Transient Voltage 1ġ Applies to all signal pins with the exception of CLKIN, XTAL, VROUT1–0.Ģ Only one of the listed options can apply to a particular design. For other duty cycles see Table 10.Ģ For proper SDRAM controller operation, the maximum load capacitance is 50 pF (at 3.3 V) or 30 pF (at 2.5 V) for ADDR19–1, DATA15–0, ABE1–0/SDQM1–0,ĬLKOUT, SCKE, SA10, SRAS, SCAS, SWE, and SMS. Īpplies to output and bidirectional pins.Īpplies to input pins except JTAG inputs.Īpplies to JTAG input pins (TCK, TDI, TMS,ġ0 See Estimating Power for ADSP-BF531/BF532/BF533 Blackfin Processors (EE-229) on the Analog Devices website ( )-use site search on “EE-229.” 11 Processor executing 75% dual MAC, 25% ADD with moderate data bus activity.ġ Applies to 100% transient duty cycle. Īpplies to all 500 MHz, 533 MHz, and 600 MHz speed grade models. V DDINT = 1.3 V, f CCLK = 600 MHz, T JUNCTION = 25☌Īpplies to all 400 MHz speed grade models. V DDINT = 1.2 V, f CCLK = 533 MHz, T JUNCTION = 25☌ V DDINT = 1.2 V, f CCLK = 500 MHz, T JUNCTION = 25☌
V DDINT = 1.14 V, f CCLK = 400 MHz, T JUNCTION = 25☌ V DDINT = 0.8 V, f CCLK = 50 MHz, T JUNCTION = 25☌ V DDINT = 0.8 V, T JUNCTION = 25☌, SCLK = 25 MHz With voltage regulator off (V DDINT = 0 V) Three-State Leakage Current V DDEXT = Maximum, V IN = 0 Vį IN = 1 MHz, T AMBIENT = 25☌, V IN = 2.5 V Three-State Leakage Current V DDEXT = Maximum, V IN = V DD Maximum Low Level Input Current V DDEXT = Maximum, V IN = 0 V High Level Input Current JTAG V DDEXT = Maximum, V IN = V DD Maximum High Level Input Current V DDEXT = Maximum, V IN = V DD Maximum Low Level Output Voltage V DDEXT = 2.25 V/3.0 V, I OL = 2.0 mA Low Level Output Voltage V DDEXT = 1.75 V, I OL = 2.0 mA High Level Output Voltage V DDEXT = 3.0 V, I OH = –0.5 mA High Level Output Voltage V DDEXT = 2.25 V, I OH = –0.5 mA High Level Output Voltage V DDEXT = 1.75 V, I OH = –0.5 mA This 3.3 V tolerance applies to bidirectional pins (DATA15–0, TMR2–0, PF15–0, PPI3–0, RSCLK1–0, TSCLK1–0, RFS1–0, TFS1–0, MOSI, MISO, SCK) and input only pins (BR, ARDY, PPI_CLK, DR0PRI, DR0SEC, DR1PRI, DR1SEC, RX, RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE1–0).Ħ Applies to all input and bidirectional pins.ĪDSP-BF531/ADSP-BF532/ADSP-BF533 ELECTRICAL CHARACTERISTICS Nonautomotive 533 MHz speed grade models 2ġ60-Ball Chip Scale Ball Grid Array (CSP_BGA) T AMBIENT = 0☌ to +70☌ġ60-Ball Chip Scale Ball Grid Array (CSP_BGA) T AMBIENT = –40☌ to +85☌ġ60-Ball Chip Scale Ball Grid Array (CSP_BGA) T AMBIENT = –40☌ to +105☌ġ69-Ball Plastic Ball Grid Array (PBGA) T AMBIENT = –40☌ to +105☌ġ69-Ball Plastic Ball Grid Array (PBGA) T AMBIENT = –40☌ to +85☌ġ76-Lead Quad Flatpack (LQFP) T AMBIENT = –40☌ to +85☌ġ The regulator can generate V DDINT at levels of 0.85 V to 1.2 V with –5% to +10% tolerance, 1.25 V with–4% to +10% tolerance, and 1.3 V with –0% to +10% tolerance.ģ Applies to all input and bidirectional pins except CLKIN.Ĥ The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are 3.3 V tolerant (always accepts up to 3.6 V maximum V IH), but voltage compliance (on outputs, V OH) depends on the input V DDEXT, because V OH (maximum) approximately equals V DDEXT (maximum). Nonautomotive 400 MHz and 500 MHz speed grade models 2
General-Purpose I/O Port F Pin Cycle TimingĪDSP-BF531/ADSP-BF532/ADSP-BF533 SPECIFICATIONSĬomponent specifications are subject to change without notice.External Port Bus Request and Grant Cycle Timing.Designing an Emulator-Compatible Processor Board.ADSP-BF531/ADSP-BF532/ADSP-BF533 Processor Peripherals.